• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    SUMMARY OF THE INVENTION The present invention provides a semiconductor integrated circuit having a filter that can suppress a product ratio as low as possible even if there is a production variation of the resistor and the capacitor that constitute the filter by adjusting the cutoff frequency. (12 to 17), the capacitor 30 to 27 consisting of the capacitance value switching circuit 75 for changing the capacitance value, and the filter 30 composed of the operational amplifiers 6 and 7, and the capacitor and resistance element of the filter. And a time constant detection circuit 180 for detecting time constants of the capacitor 133 and the resistance element 108 formed separately from each other, and change the capacitance of the capacitor based on the detected time constant.
    公开号:KR20030074090A
    申请号:KR1020020068031
    申请日:2002-11-05
    公开日:2003-09-19
    发明作者:야마모토세이지；가노겐지
    申请人:미쓰비시덴키 가부시키가이샤；
    IPC主号:
    专利说明:

    Semiconductor Integrated Circuits with Filters {FILTER-EQUIPPED SEMICONDUCTOR INTEGRATED CIRCUIT}
    [28] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit equipped with a filter, and by adjusting the cutoff frequency, a filter capable of suppressing a product ratio can be suppressed as long as the product ratio can be reduced even if there is a manufacturing variation of the resistance element and the capacitor which constitute the filter. It relates to a semiconductor integrated circuit.
    [29] FIG. 7 is a diagram showing a semiconductor integrated circuit equipped with a conventional filter described in Japanese Patent Application Laid-Open No. 61-189718, for example. In FIG. 7, reference numeral 201 denotes a differential operational amplifier and reference numeral 202 denotes a differential operational amplifier. It is a resistance element connected to the inverting input terminal of 201. Reference numeral 203 denotes a resistor element connected between the inverting input terminal and the output terminal of the differential operational amplifier 201, and reference numeral 204 denotes a capacitor element connected in parallel with the resistor 203.
    [30] Next, the operation will be described.
    [31] The filter shown in FIG. 7 is a well-known primary active filter, and the cutoff frequency is
    [32]
    [33] R f is a resistance value of the resistance element 203, and C f is a capacitance value of the capacitor 204.
    [34] Since a semiconductor integrated circuit equipped with a conventional filter is configured as described above, the cutoff frequency is shifted due to the manufacturing variation of the resistance element and the capacitance element constituting the filter, which may result in a defective product without satisfying the cutoff frequency standard. There was.
    [35] SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by adjusting the cutoff frequency, a filter capable of suppressing the product ratio can be suppressed as long as the product ratio can be reduced even if there is a production variation of the resistance element and the capacitance element constituting the filter. It is an object to obtain a mounted semiconductor integrated circuit.
    [1] 1 is a diagram illustrating a fifth-order Butterworth differential filter circuit according to Embodiment 1 of the present invention;
    [2] 2 is a diagram showing a capacitance value switching circuit 75 for changing a capacitance value according to Embodiment 1 of the present invention;
    [3] 3 is a diagram showing a layout of a capacitance value switching circuit 75 according to Embodiment 2 of the present invention;
    [4] 4 is a diagram showing a layout of a filter circuit according to Embodiment 3 of the present invention;
    [5] 5 is a diagram showing a bias circuit for an operational amplifier according to a fourth embodiment of the present invention;
    [6] 6 is a view showing a time constant detection circuit according to a fifth embodiment of the present invention;
    [7] 7 shows a semiconductor integrated circuit equipped with a conventional filter.
    [8] Explanation of symbols for the main parts of the drawings
    [9] 1, 2: input terminal 3, 4: output terminal
    [10] 5 input terminal 6, 7 differential operational amplifier
    [11] 8 to 21 resistive elements 22 to 29 capacitors
    [12] 30, 31: secondary filter 40: input terminal
    [13] 41: output terminals 42 to 46: input terminals for capacitance switching
    [14] 47-51: Inverters 52-56: P-channel transistors
    [15] 57 to 61 N-channel transistors 62 to 67 capacitor
    [16] 80: output terminal 81 to 83: resistance element
    [17] 84 to 87 P-channel transistors 88, 89 N-channel transistors
    [18] 90 N-channel transistor 91 Capacitive element
    [19] 93: power supply terminal 94: GND terminal
    [20] 100: input terminal 101: output terminal
    [21] 102 to 107: input terminals 108 to 110: resistance element
    [22] 111 to 113 capacitive elements 114 to 117 inverter
    [23] 118-124: P-channel transistor 125-130: N-channel transistor
    [24] 131: power supply terminal 132: GND terminal
    [25] 133: capacitance value switching circuit 134: node A
    [26] 201: differential operational amplifier 202, 203: resistive element
    [27] 204 capacitive element
    [36] A semiconductor integrated circuit equipped with a filter according to the present invention includes a filter including a capacitor and an operational amplifier comprising a resistor, a capacitor switching device for changing a capacitor, a capacitor corresponding to the capacitor and the resistor, It has a time constant detection circuit which detects the time constant of a resistance element, and changes the capacitance value of a capacitor based on the detected time constant.
    [37] The semiconductor integrated circuit equipped with the filter according to the present invention further has an op amp bias circuit for changing the GB product of the operational amplifier, and changes the GB product based on the detected time constant.
    [38] In a semiconductor integrated circuit having a filter according to the present invention, a time constant is stored in a fuse circuit.
    [39] In a semiconductor integrated circuit having a filter according to the present invention, the capacitor has a rectangular layout.
    [40] In a semiconductor integrated circuit having a filter according to the present invention, the resistance element is arranged in consideration of the characteristics of the filter.
    [41] In the semiconductor integrated circuit equipped with the filter according to the present invention, wiring between capacitors, resistors, and transistors constituting the time constant detection circuit is performed so as to reduce the parasitic capacitance of the time constant detection circuit, and the dimensions of the transistors are set.
    [42] Hereinafter, an embodiment of the present invention will be described.
    [43] (Example 1)
    [44] 1 is a diagram illustrating a fifth-order Butterworth differential filter circuit according to Embodiment 1 of the present invention. In Fig. 1, reference numerals 30 and 31 denote secondary filters, respectively, and the secondary filter 31 has a configuration similar to that of the secondary filter 30. Reference numerals 1 (VIP) and 2 (VIN) are input terminals to which differential input signals are input. Reference numerals 3 (OUTM) and 4 (OUTP) are output terminals to which differential output signals are output. Reference numerals 18 to 21 denote resistor elements, reference numerals 28 and 29 denote capacitor elements, and the resistor element 18, the resistor element 20, and the capacitor element 28 constitute a primary filter, and the resistor element 19, The resistor element 21 and the capacitor 29 constitute a primary filter. 5 is an input terminal of a bias voltage, 6 and 7 are differential operational amplifiers, 8-17 are resistance elements, and 22-27 are capacitive elements. The cutoff frequency is adjusted by switching capacitance values of capacitors 24 to 29. In addition, the op amp bias circuit 70 and the time constant detection circuit 180 of FIG. 1 are mentioned later.
    [45] Next, the connection will be described.
    [46] The input terminal 1 (VIP) is connected to one terminal of the capacitor 22, the resistor 8, and the resistor 10. The other terminals of the capacitor 22 and the resistor 8 are connected to GND. The other terminal of the resistive element 10 is connected to the non-inverting input of the differential operational amplifier 6. The input terminal 2 (VIN) is connected to one terminal of the capacitor 23, the resistor 9, and the resistor 11. The other terminals of the capacitor 23 and the resistor 9 are connected to GND. The other terminal of the resistance element 11 is connected to the inverting input of the differential operational amplifier 6.
    [47] One terminal of the resistive element 12 and the capacitor 24 is connected to the non-inverting input of the differential operational amplifier 6, and the other terminal of the resistive element 12 is the non-inverted output of the differential operational amplifier 7. The other terminal of the capacitor 24 is connected to the inverting output of the differential operational amplifier 6. One terminal of the resistive element 13 and the capacitor 25 is connected to the inverting input of the differential operational amplifier 6, and the other terminal of the resistive element 13 is connected to the inverting output of the differential operational amplifier 7. The other terminal of the capacitor 25 is connected to the non-inverting output of the differential operational amplifier 6.
    [48] One terminal of the resistive element 14 is connected to the inverting output of the differential operational amplifier 6, and the other terminal of the resistive element 14 is connected to the non-inverting input of the differential operational amplifier 7. One terminal of the resistance element 15 is connected to the non-inverting output of the differential operational amplifier 6, and the other terminal of the resistance element 15 is connected to the inverting input of the differential operational amplifier 7.
    [49] One terminal of the resistive element 16 and the capacitor 26 is connected to the non-inverting input of the differential operational amplifier 7, and the other terminal of the resistive element 16 and the capacitor 26 is connected to the differential operational amplifier ( It is connected to the inverting output of 7). One terminal of the resistive element 17 and the capacitor 27 is connected to the inverting input of the differential operational amplifier 7, and the other terminal of the resistive element 17 and the capacitor 27 is connected to the differential operational amplifier 7. ) Is connected to the non-inverting output of.
    [50] The input terminal 5 (GBI) is connected to the bias voltage inputs of the differential operational amplifiers 6 and 7. One terminal of the resistive element 18 is connected to the inverting output of the differential operational amplifier 7. One terminal of the resistive element 19 is connected to the non-inverting output of the differential operational amplifier 7. The other terminal of the resistance element 18 is connected to one terminal of the capacitor 28. The other terminal of the resistance element 19 is connected to one terminal of the capacitor 29. The other terminal of the capacitor 28 is connected to GND, and the other terminal of the capacitor 29 is connected to GND.
    [51] One terminal of the resistance element 20 is connected to one terminal of the capacitor 28, and the other terminal of the resistance element 20 is connected to one input terminal of the secondary filter 31. One terminal of the resistive element 21 is connected to one terminal of the capacitor 29 and the other terminal of the resistive element 21 is connected to the other input terminal of the secondary filter 31. One output terminal of the difference filter 31 is connected to the output terminal 3 (OUTM), and the other output terminal of the secondary filter 31 is connected to the output terminal 4 (OUTP).
    [52] Next, the operation will be described.
    [53] Here, the adjustment operation of the cutoff frequency by the secondary filter 30 of FIG. 1 is demonstrated. In the secondary filter 30 of FIG. 1, the capacitor 22 and the capacitor 23 are stabilizing capacitors, the resistor 8 and the resistor 9 are resistors for input signal amplitude adjustment, and a secondary filter. The circuit that operates as a circuit is a circuit other than the capacitor 22, the capacitor 23, the resistor 8, and the resistor 9. Here, the resistance of the resistors 10 to 13 is R1, the resistance of the resistors 16, 17 is R2, the resistance of the resistors 14, 15 is R4, and the capacitance of the capacitors 24, 25 is shown. When the value is C1 and the capacitances of the capacitors 26 and 27 are set to C2, the cutoff frequency f c is
    [54]
    [55] Is applied by. Therefore, the cutoff frequency f c can be adjusted by switching capacitance values C1 and C2.
    [56] 2 is a diagram showing a circuit 75 for changing the capacitance value according to the first embodiment of the present invention. The capacitor switching circuit of FIG. 2 constitutes each of the capacitors 24 to 29 of FIG. In Fig. 2, reference numeral 40 (IN) denotes an input terminal of the capacitors 24 to 29, and reference numeral 41 (OUT) denotes an output terminal of the capacitors 24 to 29 (Fig. 1). Reference numerals 42 (C0) to 46 (C4) denote capacitive switching input terminals. Reference numerals 52 to 56 denote P-channel transistors, reference numerals 57 to 61 denote N-channel transistors, and a switch for switching the capacitance value is configured by the corresponding P-channel transistor and the N-channel transistor. Reference numerals 62 to 67 denote capacitive elements. Reference numerals 47 to 51 are inverters.
    [57] Next, the connection will be described.
    [58] The input terminal 40 (IN) is connected to one terminal of the capacitor 62 and the output terminal 41 (OUT) is connected to the other terminal of the capacitor 62.
    [59] The pair of P-channel transistors 52 and N-channel transistors 57 constituting the switch are connected to respective sources and drains, the source is connected to the input terminal 40 (IN) of the capacitor, and the drain is It is connected to one terminal of the capacitor 63. The capacitor switching input terminal 42 (C0) is connected to the gate of the N-channel transistor 57 and the input terminal of the inverter 47. The output terminal of the inverter 47 is connected to the gate of the P channel transistor 52. The other terminal of the capacitor 63 is connected to the output terminal 41 (OUT).
    [60] The pair of P-channel transistors 53 and N-channel transistors 58 constituting the switch are connected to respective sources and drains, the source is connected to the input terminal 40 (IN) of the capacitor, and the drain is It is connected to one terminal of the capacitor 64. The capacitor switching input terminal 43 (C1) is connected to the gate of the N-channel transistor 58 and the input terminal of the inverter 48. The output terminal of the inverter 48 is connected to the gate of the P channel transistor 53. The other terminal of the capacitor 64 is connected to the output terminal 41 (OUT).
    [61] The pair of P-channel transistors 54 and N-channel transistors 59 constituting the switch are connected to respective sources and drains, the source is connected to the input terminal 40 (IN) of the capacitor, and the drain is It is connected to one terminal of the capacitor 65. The capacitor switching input terminal 44 (C2) is connected to the gate of the N-channel transistor 59 and the input terminal of the inverter 49. The output terminal of the inverter 49 is connected to the gate of the P channel transistor 54. The other terminal of the capacitor 65 is connected to the output terminal 41 (OUT).
    [62] The pair of P-channel transistors 55 and the N-channel transistors 60 constituting the switch are connected to respective sources and drains, the source is connected to the input terminal 40 (IN) of the capacitor, and the drain is It is connected to one terminal of the capacitor 66. The capacitance switching input terminal 45 (C3) is connected to the gate of the N-channel transistor 60 and the input terminal of the inverter 50. The output terminal of the inverter 50 is connected to the gate of the P channel transistor 55. The other terminal of the capacitor 66 is connected to the output terminal 41 (OUT).
    [63] The pair of P-channel transistors 56 and N-channel transistors 61 constituting the switch are connected to respective sources and drains, the source is connected to the input terminal 40 (IN) of the capacitor, and the drain is It is connected to one terminal of the capacitor 67. The capacitance switching input terminal 46 (C4) is connected to the gate of the N-channel transistor 61 and the input terminal of the inverter 51. The output terminal of the inverter 51 is connected to the gate of the P channel transistor 56. The other terminal of the capacitor 67 is connected to the output terminal 41 (OUT).
    [64] Next, the capacitance switching operation of the capacitors 24 to 29 (Fig. 1) will be described.
    [65] In FIG. 2, the capacitance switching input is input to each of the capacitance switching input terminals 42 (C0) to 46 (C4), and the capacitance control input terminals 42 (C0 to 46 (C4)) are input. The capacitors 63 to 67 connected to the switches in the conducting state are the capacitors 62 by bringing the pair of P-channel transistors and the N-channel transistors constituting the switch connected to the connection into either the conducting state or the non-conducting state. ) Is connected in parallel to change the capacitance of the capacitors 24 to 29 (FIG. 1).
    [66] As described above, the semiconductor integrated circuit having the filter according to the first embodiment includes the resistance elements 10 to 17 constituting the filter 30 and the capacitance value switching circuit 75 (for changing the capacitance value of the capacitor) ( The capacitors 24 to 27 formed in FIG. 2 and the operational amplifiers 6 and 7 are provided.
    [67] As described above, according to the first embodiment, since the capacitance value of the capacitors constituting the filter is changed using the capacitance value switching circuit, the effect of adjusting the cutoff frequency is obtained.
    [68] (Example 2)
    [69] 3 is a diagram showing the layout of the capacitance value switching circuit 75 (FIG. 2) according to the second embodiment of the present invention. In Fig. 3, reference numerals 52 to 56 denote P-channel transistors, and reference numerals 57 to 61 denote N-channel transistors. Reference numerals 62 to 67 denote capacitive elements for switching capacitance values. Reference numeral 40 is an input terminal, and reference numeral 41 is an output terminal. The switch for switching the capacitance value is constituted by the P channel transistors 52 to 56 and the N channel transistors 57 to 61.
    [70] Next, the shapes of the capacitors 62 to 67 will be described.
    [71] In Fig. 3, the input side of the capacitors 62 to 67 is connected to the input terminal 40 (IN) (see Fig. 2), and the output side of the capacitors 62 to 67 is connected to the output terminal 41 (OUT) ( 2). Here, since the input-output resistance of the capacitors 62 to 67 causes the deviation of the desired filter characteristic, the capacitors 62 to 67 are used to reduce the resistance between the input and output of the capacitors 62 to 67. Let the shape of) be rectangular. For example, when the MOS capacitance is used for the capacitors 62 to 67, the sheet resistance value is about several hundred Ω. 3, the capacitors 62 to 67 having a rectangular shape have a thickness along a direction perpendicular to the surface of FIG.
    [72] As mentioned above, although Example 2 was demonstrated as a layout of the capacitance value switching circuit 75 (FIG. 2) of Example 1, this Example 2 is a layout of the capacitance value switching circuit of Example 3-Example 10 mentioned later. It may be.
    [73] As described above, in the semiconductor integrated circuit having the filter according to the second embodiment, the capacitors 62 to 67 have a rectangular layout.
    [74] As described above, according to the second embodiment, since the shape of the capacitive element constituting the filter is made rectangular, the effect of reducing the resistance between the input and output of the capacitive element and preventing the deviation of the filter characteristics is obtained.
    [75] (Example 3)
    [76] 4 is a diagram showing the layout of a filter circuit (FIG. 1) according to the third embodiment of the present invention. In Fig. 4, reference numerals 6 and 7 denote differential operational amplifiers, reference numerals 8 to 21 denote resistance elements, and reference numerals 22 to 29 denote capacitive elements. The differential operational amplifiers 6 and 7 are arranged near the center, the resistive elements 8 to 21 are arranged around the differential operational amplifiers 6 and 7, and the capacitive elements (around the resistive elements 8 to 21). 22 to 29 are arranged to form a filter circuit.
    [77] Next, the arrangement of the resistance elements 8 to 21 will be described.
    [78] The filter circuit of FIG. 1 has a primary filter composed of a secondary filter 30, a secondary filter 31, resistance elements 18 to 21, and capacitor elements 28 and 29. In FIG. 4, the resistance elements 10, 12, 14, and 16 constituting the secondary filter 30 are disposed near each other, and the resistance elements 11, 13, 15, and 17 constituting the secondary filter 30. ) Are placed near each other, the resistance elements 18 and 20 constituting the primary filter are disposed close to each other, and the resistance elements 19 and 21 constituting the primary filter are arranged near each other. Get the characteristics.
    [79] This is because in the filter circuit of FIG. 1, the Q of the filter circuit is determined by the ratio of the resistance value of the resistance element and the capacitance value of the capacitance element, so that the differential operational amplifier, the resistance element and the capacitance element are disposed by placing the resistance element constituting the filter in the vicinity. By shortening the wiring elements for connecting the gaps, Q can be made the desired value by making the resistance value and the capacitance value resulting from the wiring elements as small as possible. For example, Q of the secondary filter 30 of the filter circuit of FIG.
    [80]
    [81] Is applied by.
    [82] Although the third embodiment has been described as the layout of the filter circuit of the first embodiment, the third embodiment may be the layout of the filter circuits of the second embodiment and the fourth to tenth embodiments described later.
    [83] As described above, in the semiconductor integrated circuit having the filter according to the third embodiment, the resistor elements 10 to 21 are arranged in consideration of filter characteristics.
    [84] As described above, according to the third embodiment, a wiring element for connecting the differential operational amplifier, the resistance element and the capacitor element is shortened by disposing the resistance element constituting the filter in the vicinity, thereby resulting from the wiring element. The effect of making Q desired by the ratio of the resistance value of the resistance element and the capacitance value of the capacitor element to be a desired value is obtained by making the resistance value and the capacitance value as small as possible.
    [85] (Example 4)
    [86] 5 is a diagram showing a bias circuit 70 for an operational amplifier according to a fourth embodiment of the present invention. In Fig. 5, reference numeral 80 denotes an output terminal, reference numeral 81 denotes a resistance element, reference numerals 82 and 83 denote a resistance element, reference numerals 84-87 denote P-channel transistors, and reference numerals 88-90 denote N-channel transistors. Reference numeral 91 is a capacitor. Reference numeral 93 is a power supply terminal, and reference numeral 94 is a GND terminal.
    [87] By switching the resistance value of the resistance element 81, the bias voltages for the differential operational amplifiers 6 and 7 output from the output terminal 80 (GBI) can be adjusted. The op amp bias circuit 70 shown in FIG. 5 is a circuit for adjusting the GB product of the differential op amps 6 and 7 constituting the filter circuit of FIG.
    [88] Next, the connection will be described.
    [89] One terminal of the resistance element 82 is connected to the power supply terminal 93, and the other terminal of the resistance element 82 is connected to one terminal of the resistance element 83. The other terminal of the resistance element 83 is connected to the GND terminal 94. The drain of the P channel transistor 84 is connected to the power supply terminal 93, the source of the P channel transistor 84 is connected to the drain of the P channel transistor 86 and one terminal of the resistance element 81, and P The gate of the channel transistor 84 is connected to the gate and the source of the P channel transistor 85.
    [90] The source of the P channel transistor 86 is connected to the source and gate of the N channel transistor 88. The gate of the P-channel transistor 86 is connected to one terminal of the resistance element 83. The drain of the N-channel transistor 88 is connected to the GND terminal 94, and the gate of the N-channel transistor 88 is connected to the gate of the N-channel transistor 89.
    [91] The drain of the P-channel transistor 87 is connected to the other terminal of the resistor element 81, and the source of the P-channel transistor 87 is connected to the source and output terminal 80 (GBI) of the N-channel transistor 89. The gate of the P-channel transistor 87 is connected to one terminal of the resistance element 83. The drain of the N-channel transistor 89 is connected to the GND terminal 94.
    [92] The drain of the P channel transistor 85 is connected to the power supply terminal 93, and the source of the P channel transistor 85 is connected to the source of the N channel transistor 90. The drain of the N-channel transistor 90 is connected to the GND terminal 94, and the gate of the N-channel transistor 90 is connected to the output terminal 80 (GBI). One terminal of the capacitor 91 is connected to the output terminal 80 (GBI), and the other terminal of the capacitor 91 is connected to the GND terminal 94.
    [93] Next, the operation will be described.
    [94] In Example 1, the bias circuit for the operational amplifier of FIG. 5 in order to adjust the cutoff frequency f c by changing the capacitance value of the capacitor even if there is a manufacturing variation of the resistor and the capacitor constituting the filter circuit of FIG. Use
    [95] 1 and 5, the differential operational amplifiers 6 and 7 are changed by changing the capacitance value of the capacitor element in order to adjust the cutoff frequency f c and switching the resistance value of the resistor element 81 in FIG. Adjust your GB enemy accordingly.
    [96] Specifically, the GB product of the differential operational amplifiers 6 and 7 shown in FIG. 1 is defined as 1 / (R × C c ) (R: resistance value of the resistor element 81, C c : differential operational amplifiers 6 and 7). The bias circuit for the operational amplifier of FIG. 5 is configured to be proportional to the phase compensation capacitance (capacitance value is fixed) built in the circuit.
    [97] As described above, the semiconductor integrated circuit equipped with the filter according to the fourth embodiment further has an op amp bias circuit 70 (Fig. 5) for changing the GB product of the op amp.
    [98] As described above, according to the fourth embodiment, by adjusting the GB product of the differential operational amplifier appropriately by using the op amp bias circuit, the capacitance value of the capacitive element can be adjusted even if there are variations in the manufacturing of the resistance element and the capacitor constituting the filter. By changing, the effect which can adjust a cutoff frequency is acquired.
    [99] (Example 5)
    [100] 6 is a diagram showing a time constant detection circuit 180 according to Embodiment 5 of the present invention. In Fig. 6, reference numeral 100 is an input terminal, reference numeral 101 is an output terminal, reference numerals 102-107 are input terminals, reference numerals 108-110 are resistance elements, reference numerals 111-113 are capacitive elements, Reference numerals 114 to 117 denote inverters, reference numerals 118 to 124 denote P-channel transistors, reference numerals 125 to 130 denote N-channel transistors, reference numeral 131 denotes power terminals, reference numeral 132 denotes GND terminals, reference numeral 133 Denotes a capacitance value switching circuit shown in Fig. 2, and reference numeral 134 denotes a node A. Figs. The time constant detection circuit 180 determines the time constants of the capacitance value switching circuit 133 and the resistance element 108 by sequentially switching the capacitance values of the capacitance value switching circuit 133 to output the output terminal 101. Output as an output signal from (CMPOUT). This output signal is supplied to the trimming device 150. The trimming device 150 melts the fuse of the fuse circuit 160 in accordance with the output signal, or maintains the connection state as it is. The capacitor value switching circuit 133 used in FIG. 6 is an element having the same shape and the same configuration as the capacitor element constituting the filter circuit of FIG. 1, and is formed separately from the capacitor element constituting the filter circuit for capacitance value detection. .
    [101] Next, the connection will be described.
    [102] One terminal of the resistance element 108 is connected to the power supply terminal 131, and the other terminal of the resistance element 108 is connected to the node A 134. The node A 134 is connected to one terminal of the capacitor value switching circuit 133 (output terminal 41 (OUT) in FIG. 2) and the drain of the P channel transistor 118. The other terminal (input terminal 40 (IN) in FIG. 2) of the capacitance value switching circuit 133 is connected to the GND terminal 132.
    [103] The source of the P channel transistor 118 is connected to the GND terminal 132, and the gate of the P channel transistor 118 is connected to the input terminal 100 (EDC). One terminal of the resistance element 109 is connected to the power supply terminal 131, and the other terminal of the resistance element 109 is connected to one terminal of the resistance element 110 and one terminal of the capacitor 111. It is. The other terminal of the resistance element 110 and the other terminal of the capacitor 111 are connected to the GND terminal 132.
    [104] The source of the P channel transistor 119 and the source of the N channel transistor 125 are connected to the node A 134. The drain of the P-channel transistor 119 and the drain of the N-channel transistor 125 are connected to one terminal of the capacitor 112. The gate of the P-channel transistor 119 is connected to the input terminal 102 (CNI), and the gate of the N-channel transistor 125 is connected to the input terminal 103 (CPI).
    [105] The source of the P channel transistor 120 and the source of the N channel transistor 126 are connected to the other terminal of the resistor element 109, and the drain of the P channel transistor 120 and the drain of the N channel transistor 126 are capacitances. It is connected to one terminal of the element 112. The gate of the P-channel transistor is connected to the input terminal 104 (RNI), and the gate of the N-channel transistor is connected to the input terminal 105 (RPI).
    [106] The source of the P channel transistor 121 and the source of the N channel transistor 127 are connected to the other terminal of the capacitor element 112, and the drain of the P channel transistor 121 and the drain of the N channel transistor 127 are capacitors. It is connected to one terminal of the element 113. The gate of the P-channel transistor 121 is connected to the input terminal 106 (HNI), and the gate of the N-channel transistor 127 is connected to the input terminal 107 (HPI). The input terminal of the inverter 114 is connected to the other terminal of the capacitor 112, and the output terminal of the inverter 114 is connected to one terminal of the capacitor 113.
    [107] The source of the P channel transistor 122 and the source of the N channel transistor 128 are connected to the other terminal of the capacitor element 113, and the drain of the P channel transistor 122 and the drain of the N channel transistor 128 are inverters. It is connected to the output terminal of 115. The gate of the P-channel transistor 122 is connected to the input terminal 106 (HNI), and the gate of the N-channel transistor 128 is connected to the input terminal 107 (HPI). The input terminal of the inverter 115 is connected to the other terminal of the capacitor 113.
    [108] The source of the P-channel transistor 123 and the source of the N-channel transistor 129 are connected to the output terminal of the inverter 115. The drain of the P-channel transistor 123 and the drain of the N-channel transistor 129 are connected to the input terminal of the inverter 116. The gate of the P-channel transistor 122 is connected to the input terminal 102 (CNI), and the gate of the N-channel transistor 129 is connected to the input terminal 103 (CPI).
    [109] The source of the P channel transistor 124 and the source of the N channel transistor 130 are connected to the input terminal of the inverter 116, and the drain of the P channel transistor 124 and the drain of the N channel transistor 130 are output terminals ( 101) (CMPOUT). The gate of the P-channel transistor 124 is connected to the input terminal 103 (CPI), and the gate of the N-channel transistor 130 is connected to the input terminal 102 (CNI). The input terminal of the inverter 117 is connected to the output terminal of the inverter 116, and the output terminal of the inverter 117 is connected to the output terminal 101 (CMPOUT).
    [110] Next, the operation will be described.
    [111] In Fig. 6, the switching sequence of the capacitance value of the capacitance value switching circuit 133 is as follows. In this case, the capacitance value switching terminal of the capacitance value switching circuit 133 of FIG. 2 has five terminals, and the time constant is determined five times. When the capacitance value switching range of the capacitance value switching circuit 133 is set to C max -C min , the first capacitance value of the capacitance value switching circuit 133 is set to the center capacitance value C max -C min of the capacitance switching range. / 2 is set to determine the time constant of the capacitance value switching circuit 133 and the resistance element 108 and the magnitude of the reference time constant, and the second time is (C max -C min ) / 2 and C max or C The magnitude of both time constants is determined by setting the center capacitance value of min , and this is performed up to five times. Here, the capacitance value to be set does not need to be exactly (C max -C min ) / 2, but may be an appropriate value between C max and C min .
    [112] The capacitance values of the capacitors 62 to 67 in Fig. 2 are, for example, a capacitor 62: 5.5 Hz, a capacitor 63: 0.25 Hz, a capacitor 64: 0.5 Hz, and a capacitor 65: The capacitance element 66 is 2.0 Hz and the capacitance element 67 is 3.0 Hz. In this case, the capacitance value switching range C max to C min is 12.25 μs to 0.25 μs, and the center capacitance value (C max −C min ) / 2 of the capacitance value switching is 6.00 μs.
    [113] In the time constant detection circuit 180 of FIG. 6, the signal input to the input terminal 106 is removed from H (the signal input to the input terminal 107 is L), and is input to the input terminal 104. The voltage (reference voltage) Vref that the signal is compared at H (the signal input to the input terminal 105 is L) is charged to the capacitive element 112 through the resistance element 109 and input to the input terminal 102. The comparison operation starts at the signal H (the signal input to the input terminal 103 is L). The signal output from the output terminal 101 is H when the voltage of the node A 134 is higher than the reference voltage Vref charged to the capacitor 112, and when the voltage of the node A 134 is lower than the reference voltage Vref. Becomes L. At the time of capacitance switching, the signal input to the input terminal 102 is L (the signal input to the input terminal 103 is H), and the signal input to the input terminal 104 is input to the L (the input terminal 105). The signal is input to H) and the signal input to the input terminal 106 is L (the signal input to the input terminal 107 is H).
    [114] The capacitors of the capacitor value switching circuit 133 selected by the first determination are, for example, the capacitor 62 and the capacitor 67 (5.5 m + 3.0 m = 8.5 m). As a result of comparing the voltage Va of the node A 134 and the reference voltage Vref, the voltage Va of the node A 134 is output from the output terminal 101 lower than the reference voltage Vref, so that the signal is L.
    [115] Since the signal from the output terminal 101 as the result of the first determination is L, the capacitor selected by the second determination includes the capacitor 62 and the capacitor 65 (5.5 Hz + 1.0 Hz = 6.5 Hz). ). As a result of comparing the voltage Va of the node A 134 with the reference voltage Vref, the voltage Va of the node A 134 is output from the output terminal 101 higher than the reference voltage Vref, so that the signal is H.
    [116] Since the signal from the output terminal 101 which is the result of the second determination is H, the capacitor selected by the third determination is the capacitor 62 and the capacitor 66 (5.5 kHz + 2.0 kHz = 7.5 kHz). It becomes As a result of comparing the voltage Va of the node A 134 with the reference voltage Vref, the voltage Va of the node A 134 is output from the output terminal 101 lower than the reference voltage Vref, so that the signal is L.
    [117] Since the signal from the output terminal 101 as the result of the third determination is L, the capacitor selected by the fourth determination is the capacitor 62, the capacitor 64, and the capacitor 65 (5.5㎊ + 0.5 Hz + 1.0 Hz = 7.0 Hz). As a result of comparing the voltage Va of the node A 134 with the reference voltage Vref, the voltage Va of the node A 134 is output from the output terminal 101 higher than the reference voltage Vref, so that the signal is H.
    [118] Since the signal from the output terminal 101 as the result of the fourth determination is H, the capacitor selected by the fifth determination is the capacitor 62, the capacitor 63, the capacitor 64 and the capacitor ( 65) (5.5 ms + 0.5 ms + 1.0 ms + 0.25 ms = 7.25 ms).
    [119] Since the determination of the first to fifth times is determined based on the time constants of the selected capacitance element (FIG. 2) and the resistance element 108 of FIG. 6 in the capacitance value switching circuit 133 of FIG. 6, the capacitance value of FIG. The capacitance value of the selected capacitor in the switching circuit 133 is changed as described above and finally becomes 7.25 kV, correcting by setting the capacitance value -10% of the deviation value of the resistance value to + 10%. have.
    [120] The output of the output terminal 101 (CMPOUT) output as the determination result (case determination result) of each of the five determinations is stored five times by the external fuse circuit 160 via the trimming device 150. The cutoff frequency f c can be adjusted by using the stored code as a capacitance value switching code of the capacitor of the filter circuit of FIG. 1.
    [121] As described above, the semiconductor integrated circuit equipped with the filter according to the fifth embodiment includes the resistor elements 12 to 17 constituting the filter 30 and the capacitance value switching circuit for changing the capacitance value of the capacitor element (FIG. 2). The capacitors 24 to 27, op amps 6 and 7, and the capacitors 24 to 27 and the resistors 12 to 17 formed of the capacitors are formed separately and have the same shape and the same capacitance as those. It has a time constant detection circuit (FIG. 6) which detects the time constant of an element and a resistance element, and changes the capacitance value of the capacitance element of the filter 30 based on the detected time constant.
    [122] As described above, according to the fifth embodiment, since the time constant is detected by using the time constant detection circuit, an effect of easily detecting the deviation of the cutoff frequency is obtained.
    [123] (Example 6)
    [124] By using a resistance value conversion code of the resistance element 81 in FIG time constant of 6 capacitance of the capacitor element of the filter circuit of Figure 1 the information on the number of a time constant detecting in the detection circuit switch code, and Figure 5 cut-off frequency f c and the differential The GB product of the op amp can be adjusted to the optimum value.
    [125] As described above, the semiconductor integrated circuit equipped with the filter according to the sixth embodiment further includes an op amp bias circuit (Fig. 5) for changing the GB product of the operational amplifier, and changes the GB product based on the detected time constant. .
    [126] As described above, according to the sixth embodiment, since the time constant is detected by using the time constant detection circuit, the deviation of the cutoff frequency can be easily detected, and the GB product of the differential operational amplifier is adjusted according to the detected time constant. The effect can be obtained.
    [127] (Example 7)
    [128] In the fifth embodiment, when the time constant is detected by FIG. 6, the parasitic capacitance of the node A becomes the detection error of the time constant. For this reason, the wiring between the capacitor elements, the P channel transistors 118 and 119, the N channel transistor 125 and the resistance element 108 of the capacitance value switching circuit 133 is shortened and thinned so as to minimize the parasitic capacitance. In addition, the L size (gate length) of the P-channel transistors 118 and 119 and the N-channel transistor 125 is thinned to reduce the parasitic capacitance. The time constant detection circuit 180 with few errors can be obtained from the above.
    [129] As mentioned above, although this Example 7 was demonstrated as applying to the time-constant detection circuit of Example 5, this Example 7 may be applied to the time-constant detection circuit in Example 9 mentioned later.
    [130] As described above, in the semiconductor integrated circuit equipped with the filter according to the seventh embodiment, the capacitance elements 111 to 113 and the resistance elements 108 to 110 constituting the time constant detection circuit so as to reduce the parasitic capacitance of the time constant detection circuit. And the wirings between the transistors 118 to 130 are performed to set the dimensions of the transistors.
    [131] As described above, according to the seventh embodiment, a time constant detection circuit having a small error is obtained because the wiring between the capacitor, the transistor, and the resistance element is shortened and thinned, and the L size of the transistor is reduced to reduce the parasitic capacitance. An effect that can be obtained is obtained.
    [132] (Example 8)
    [133] In Example 6, when detecting time constant by FIG. 6, the parasitic capacitance of node A becomes a detection error of time constant. For this reason, the wiring between the capacitor elements, the P channel transistors 118 and 119, the N channel transistor 125 and the resistance element 108 of the capacitance value switching circuit 133 is shortened so as to make the parasitic capacitance as small as possible. The parasitic capacitance is reduced by narrowing the L size of the P-channel transistors 118 and 119 and the N-channel transistor 125. As mentioned above, the time constant detection circuit with few errors can be obtained.
    [134] As described above, the eighth embodiment has been described as being applied to the time constant detection circuit of the sixth embodiment. However, the eighth embodiment may be applied to the time constant detection circuit in the tenth embodiment described later.
    [135] As described above, in the semiconductor integrated circuit equipped with the filter according to the eighth embodiment, the capacitors 111 to 113 and the resistors 108 to 110 constituting the time constant detection circuit so as to reduce the parasitic capacitance of the time constant detection circuit. ) And the transistors 118-130 are wired, and the dimension of a transistor is set.
    [136] As described above, according to the eighth embodiment, a time constant detection circuit having a small error is obtained because the wiring between the capacitor, the transistor, and the resistor is shortened and thinned, and the L size of the transistor is reduced to reduce the parasitic capacitance. An effect that can be obtained is obtained.
    [137] (Example 9)
    [138] In the fifth embodiment, the time constant detection information detected by FIG. 6 is stored in the fuse circuit. This allows time constant detection to be pre-released and stored in the fuse circuit, eliminating the need to perform time constant detection, cutoff frequency f c adjustment, and differential adjustment of the differential operational amplifiers constituting the filter circuit in actual use. The time taken for time constant detection in actual use can be omitted.
    [139] As described above, the semiconductor integrated circuit having the filter according to the ninth embodiment stores the time constant in the fuse circuit.
    [140] As described above, according to the ninth embodiment, since the time constant detection information is stored in the fuse circuit, time constant detection, cutoff frequency adjustment, and GB adjustment of the differential operational amplifier constituting the filter circuit are performed during actual use. There is no need to do this, and the effect that time taken for time constant detection in actual use can be omitted is obtained.
    [141] (Example 10)
    [142] In the sixth embodiment, the time constant detection information detected by FIG. 6 is stored in the fuse circuit. This allows time constant detection to be pre-released and stored in the fuse circuit, eliminating the need to perform time constant detection, cut-off frequency f c adjustment, and GB adjustment of the differential operational amplifier constituting the filter circuit during actual use. The time taken for time constant detection in actual use can be omitted.
    [143] As described above, the semiconductor integrated circuit having the filter according to the tenth embodiment stores the time constant in the fuse circuit.
    [144] As described above, according to the tenth embodiment, since the time constant detection information is stored in the fuse circuit, the time constant detection, cutoff frequency adjustment, and GB adjustment of the differential operational amplifier constituting the filter circuit are performed during actual use. There is no need to do this, and the effect that time taken for time constant detection in actual use can be omitted is obtained.
    [145] As described above, according to the present invention, since the capacitance value of the capacitor constituting the filter is changed by using the capacitance value switching circuit, and the time constant is detected by the time constant detection circuit, the shift of the cutoff frequency is prevented. There is an effect that it is easy to detect and adjust the cutoff frequency.
    [146] According to the present invention, since the time constant is detected by using the time constant detection circuit, the shift of the cutoff frequency can be easily detected, and the filter is configured by appropriately adjusting the GB product of the differential operational amplifier according to the detected time constant. Even if there are variations in the manufacturing of the resistance element and the capacitor, the cutoff frequency can be adjusted by changing the capacitance of the capacitor.
    [147] According to the present invention, since the time constant detection information is stored in the fuse circuit, the time constant detection and cutoff frequency adjustment and the GB adjustment of the differential operational amplifier constituting the filter circuit are not necessary during actual use. There is an effect that the time taken to detect the time constant in use can be omitted.
    [148] According to the present invention, since the shape of the capacitors constituting the filter has a rectangular shape, the input-output resistance of the capacitors can be reduced to prevent deviation of filter characteristics.
    [149] According to the present invention, by placing a resistor element constituting the filter in the vicinity, a wiring element for connecting between the differential operational amplifier, the resistor element and the capacitor element is shortened, thereby resulting in a resistance value and a capacitance value resulting from the wiring element. As little as possible, there is an effect that Q, which is determined by the ratio of the resistance value of the resistance element and the capacitance value of the capacitor element, can be set as a desired value.
    [150] According to the present invention, since the wiring between the capacitor, the transistor, and the resistor is shorter and thinner, and the L size of the transistor is reduced to reduce the parasitic capacitance, the time constant detection circuit with less error can be obtained. have.
    权利要求:
    Claims (1)
    [1" claim-type="Currently amended] A filter comprising a resistor, a capacitor, and an operational amplifier, the capacitor comprising a filter comprising a capacitor value switching circuit for changing the capacitor value;
    It has a time constant detection circuit which detects the time constants of the capacitance element and the resistance element corresponded to the said capacitance element and the said resistance element,
    And the capacitance value of the capacitor is changed based on the detected time constant.
    类似技术:
    公开号 | 公开日 | 专利标题
    US5109261A|1992-04-28|CMOS amplifier with offset adaptation
    JP4548562B2|2010-09-22|Current mirror circuit and analog-digital conversion circuit
    US4675594A|1987-06-23|Voltage-to-current converter
    JP3841428B2|2006-11-01|Charge transfer device
    US5068622A|1991-11-26|CMOS amplifier with offset adaptation
    US7368973B2|2008-05-06|Temperature sensor circuit
    KR100432933B1|2004-05-28|Oscillator circuit and integrated circuit for oscillation
    JP4937865B2|2012-05-23|Constant voltage circuit
    US6946821B2|2005-09-20|Voltage regulator with enhanced stability
    KR900003938B1|1990-06-04|Integrated circuit having fuse circuit
    US6496049B2|2002-12-17|Semiconductor integrated circuit having a current control function
    US20160087624A1|2016-03-24|High frequency switch circuit
    US6348835B1|2002-02-19|Semiconductor device with constant current source circuit not influenced by noise
    US20020145467A1|2002-10-10|Folded floating-gate differential pair amplifier
    US9058048B2|2015-06-16|Voltage regulator having error amplifier
    US7154334B2|2006-12-26|Common mode feedback circuit for fully differential two-stage operational amplifiers
    US20040080352A1|2004-04-29|Clamp circuit
    US10020739B2|2018-07-10|Integrated current replicator and method of operating the same
    US7030686B2|2006-04-18|Constant voltage circuit with phase compensation
    US20090027086A1|2009-01-29|Comparator and method with controllable threshold and hysteresis
    US20050184805A1|2005-08-25|Differential amplifier circuit
    TWI236259B|2005-07-11|Precise slew rate control line driver
    US8536844B1|2013-09-17|Self-calibrating, stable LDO regulator
    US6670850B1|2003-12-30|Ultra-wideband constant gain CMOS amplifier
    KR100891221B1|2009-04-01|Variable gain amplifier and filter circuit
    同族专利:
    公开号 | 公开日
    US20030169101A1|2003-09-11|
    JP2003258604A|2003-09-12|
    DE10251093A1|2003-11-27|
    US6670846B2|2003-12-30|
    KR100486989B1|2005-05-03|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-03-06|Priority to JPJP-P-2002-00060818
    2002-03-06|Priority to JP2002060818A
    2002-11-05|Application filed by 미쓰비시덴키 가부시키가이샤
    2003-09-19|Publication of KR20030074090A
    2005-05-03|Application granted
    2005-05-03|Publication of KR100486989B1
    优先权:
    申请号 | 申请日 | 专利标题
    JPJP-P-2002-00060818|2002-03-06|
    JP2002060818A|JP2003258604A|2002-03-06|2002-03-06|Semiconductor integrated circuit with mounted filter|
    [返回顶部]